The present invention relates to a method of forming a mask for use in the lithography for manufacturing semiconductor devices and, more particularly, to a mask for the charged particle beam exposure which transcribes a mask pattern onto a wafer using charged particle beams such as electron beams and ion beams and to a method for forming the same.
With miniaturization and increase in integration of semiconductor elements in semiconductor integrated circuits, an electron-beam projection lithography for transcribing a predetermined configuration onto a wafer using charged particle beams, especially using electron beams, was developed instead of the conventional photolithography using light beam. Recently, the development of EPL (Electron-beam Projection Lithography) method achieving higher throughput has advanced. As an electron-beam projection lithography, there is a method in which a prescribed mask pattern is divided into a plurality of sections, stencil masks formed with opening patterns each having a predetermined size and a predetermined arrangement are prepared, and electron beams are incident on the sections so that electron beams thus formed by the opening patterns are transcribed onto a wafer as a subject substrate on some reduced scale. There has been developed a system for forming a device pattern by combining prescribed patterns separately formed on the mask onto the subject substrate (for example, see Patent Document 1).
An example of a mask used for the aforementioned electron-beam projection lithography is shown in FIGS. 8(a), 8(b). Shown in FIGS. 8(a), 8(b) is an example of a mask 70 used for the electron-beam exposure using a wafer substrate of 8 inches. FIG. 8(a) is an entire view of the mask having two pattern regions (132.57 mm×54.43 mm) 71. Each of the pattern regions 71 comprises a membrane mask pattern 72 and a strut 73 (0.17 mm in width).
The membrane mask pattern 72 is a pattern with through-holes for transmitting electron beams which are formed in a silicon membrane. Since the membrane mask pattern 72 is quite thin, a pattern region is divided and reinforced by a supporting grillage, referred to as “strut” 73 (0.17 mm in width), from the back so as to reinforce the membrane mask pattern 72, thereby reducing the distortion of the pattern region and improving the accuracy of position of the pattern region. FIG. 8(b) is a partial enlarged schematic view of FIG. 8(a). The membrane mask pattern 72 is formed in interstices of the strut 73.
Therefore, the quality and characteristics of the silicon membrane are important for the purpose of forming a mask for the charged particle beam exposure of high quality and high accuracy.
Since the silicon of the membrane side and the silicon of the strut side are subjected to etching in separate processes, an etching stop layer having a predetermined thickness is required between the silicon of the membrane side and the silicon of the strut side in the mask substrate during fabrication of the mask. Generally used as such etching stop layer is a silicon oxidized film.
As for the mask substrate for forming the aforementioned mask for the charged particle beam exposure, there is a method using an SOI (Silicon On Insulator) substrate in which a silicon membrane is formed via a silicon oxidized film on a silicon wafer and a method using a substrate on which a silicon membrane is formed by sputtering via a metallic layer on a silicon wafer.
SOI substrate is reliable because SOI substrates have been practically employed as semiconductor circuit substrates for LSI and a silicon membrane as an upper layer for fabrication of pattern possesses higher reliability in quality because the silicon membrane is single crystal and is formed with zero defects.
As the manufacturing method of SOI substrate, there are two practical methods such as a bonding method and an implanting method. There are some kinds of SOI substrates corresponding to these manufacturing methods. Some SOI substrates have been studied as mask substrates for forming masks used for the charged particle beam exposure.
As the bonding method, for example, a silicon substrate (referred to as “base wafer”) as a support substrate is subjected to thermal oxidation, a different silicon substrate (referred to as “bond wafer”) used for forming a silicon membrane layer is bonded to the base wafer, and the bond wafer is subjected to lapping and polishing whereby a significant amount of thickness is reduced, thereby forming a wafer substrate as the silicon membrane layer (for example, see Patent Document 1).
Examples of substrate according to another bonding method include a Smart Cut wafer substrate in which a thermal-oxidized wafer (bond wafer) subjected to hydrogen ion implantation is bonded to a base wafer, and an ELTRAN (Epitaxial Layer Transfer) wafer substrate in which a wafer (bond wafer) having an epitaxial layer formed thereon is bonded to a base wafer.
As an example of substrate according to the implanting method, there is an SIMOX (Separation by Implanted Oxygen) wafer substrate in which the wafer substrate is subjected to oxygen ion implantation so as to form an implanted silicon oxidized film.
However, in a mask for the charged particle beam exposure employing the SOI substrate according to the method described in Patent Document 2, the silicon membrane layer bonded on the wafer substrate is subjected to lapping and polishing so as to have a reduced thickness. Therefore, larger variation in thickness of substrate should be caused. While the desired thickness is on the order of 2 μm, there may be differences about ±0.5 μm. Accordingly, the SOI substrate has a problem that it is not suitable for practical use for masks of high accuracy. Though there is a method called PACE (Plasma Assisted Chemical Etching) as a lapping and polishing technology which can improve the distribution in thickness to ±0.1 μm, this method provide poor productivity. For example, in case of processing an SOI substrate of 200 mm in diameter to remove 3.8 μm with accuracy of ±0.1 μm, the PACE process should be conducted three times so that one hour or more is taken for one substrate.
On the other hand, as for the mask for the charged particle beam exposure employing the SOI substrate according to the other method, for example, in case of a SIMOX (Separation by Implanted Oxygen) wafer substrate in which the wafer substrate is subjected to oxygen ion implantation so as to form an implanted silicon oxidized film, the silicon oxidized film is very thin such as 0.14 μm or less. This is insufficient, as an etching stop layer during the fabrication of mask. Further, the silicon membrane layer to be a membrane is also thin such as 0.25 μm or less. A mask for the charged particle beam exposure formed using the SOI substrate has a problem that the strength of the membrane is insufficient as the mask pattern. As for the Smart Cut wafer substrate in which a thermal-oxidized wafer (bond wafer) subjected to hydrogen ion implantation is bonded to a base wafer, the silicon membrane layer to be a membrane is thin such as 0.4 μm or less. A mask for the charged particle beam exposure formed using the SOI substrate has a problem that the strength of the membrane is insufficient as the mask pattern. In the ELTRAN (Epitaxial Layer Transfer) wafer substrate in which a wafer (bond wafer) having an epitaxial layer formed thereon is bonded to a base wafer, the silicon oxidized film and the silicon membrane layer can be formed to have desired thicknesses. However, the mask for the charged particle beam exposure formed by employing this substrate has a problem of large distortion of the mask pattern due to the compressive stress (300–400 MPa in case that the thickness of SiO2 is 1 μm) of the silicon oxidized film. As one of improvement measures, there is a method of imparting tensile stress to the silicon membrane by doping impurity ion such as boron or phosphorus of which atom radius is smaller than that of silicon into the silicon membrane by ion implantation in order to reduce the stress during the formation of mask pattern. However, since the required amount to be doped is too much such as 1×1018 atoms/cm3, it takes too much time to obtain the desired doping amount by the ion implantation. This means there is a problem that it is difficult to commercially achieve practical use.
On the other hand, a method of forming a mask for the charged particle beam exposure in which a silicon membrane is formed by way of sputtering has an advantage that the etching selectivity is improved because metal can be used as an etching stop layer (for example, see non patent document 1).
However, the structure of the silicon membrane formed by way of sputtering is in amorphous state and the silicon membrane is therefore not dense. If abnormal particles of silicon are generated, defects are produced. Accordingly, it is difficult to form a silicon membrane layer without defects and having uniform thickness. Thus, there is a problem that it is hard to obtain a high quality mask using a mask blank prepared by this forming method. In addition, since electrons are scattered at boundaries crystal particles in amorphous silicon, heat may be stored in the obtained mask. Therefore, there is an essential problem that the heat deformation of the mask is inevitable during the electron-beam exposure projection.
[Patent Document 1]
Japanese Patent No. 2829942
[Patent Document 2]
Japanese Patent No. 2725319
[Non-patent Document 1]
Abstracts of The 46th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication, p401, “Fabrication of complete 8” stencil mask for electron projection lithography”.